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Circuits
8 months ago
What is the output appearance of a pulse generator circuit with a 2-input NAND gate and delayed inputs due to inverters, based on the input timing diagram?
Design Verification Engineer

Toshiba

Lattice Semiconductor

Thermo Fisher Scientific

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8 months ago
Technical
8 months ago
Could you explain the concept of a counter's modulus and the modulus of a decade counter?
Design Verification Engineer

Toshiba

Qualcomm

Microsoft

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8 months ago
Behavioral
8 months ago
Share an experience where you made a decision that wasn't universally accepted.
Design Verification EngineerEmbedded Engineer

Toshiba

Philips Healthcare Logo

Philips Healthcare

NetApp Logo

NetApp

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8 months ago
Design
9 months ago
What is the role of master and slave agents on a shared bus in systems like AXI, and how would you approach maintaining data integrity and avoiding bus contention?
Design Verification Engineer

Toshiba

Aurora Logo

Aurora

Teradyne Logo

Teradyne

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9 months ago
Chip Design
10 months ago
Craft a sequence detector to identify the pattern 101 in a serial bit stream.
Design Verification Engineer

Toshiba

Teradyne Logo

Teradyne

OMRON Logo

OMRON

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10 months ago
Technical
10 months ago
What is your understanding of polymorphism in SystemVerilog?
Design Verification Engineer

Toshiba

MediaTek Logo

MediaTek

Samsung Logo

Samsung

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10 months ago
Verilog Coding
10 months ago
How would you code an HDL FSM with IDLE, READ, and WRITE states, transitioning based on "op" signal and reverting to IDLE after 4 cycles?
Design Verification Engineer

Toshiba

NXP Semiconductors Logo

NXP Semiconductors

NVIDIA Logo

NVIDIA

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10 months ago
Technical
10 months ago
Can you differentiate between soft and hard constraints in SystemVerilog?
Design Verification Engineer

Toshiba

Canon Logo

Canon

Microchip Technology Logo

Microchip Technology

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10 months ago
Circuits
a year ago
Using the write(addr, data) and read(addr, &data) APIs only, can you explain your method to identify a shorted internal signal in a device?
Design Verification Engineer

Toshiba

Legrand Logo

Legrand

Applied Materials Logo

Applied Materials

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a year ago
Technical
a year ago
How would you outline the verification environment for Ethernet MAC IP, focusing on its various components?
Design Verification Engineer

Toshiba

Apple Logo

Apple

ASML Logo

ASML

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a year ago

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*All interview questions are submitted by recent Toshiba Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Toshiba.

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