Prepfully logo
  • Browse Coaches
  • Login
BetaTry Out Our New AI Mock Interviewer – Your Smartest Way to Ace Any Interview!Try Our AI Mock Interviewer
Try Now
NewRegister as a coach and get a $100 bonus on your first completed session if you're on the Prepfully Request for Coaches list.Coach $100 Bonus
Read More
LimitedEaster Deal: Heavy discounts on all Prepfully sessions.Easter Deal: Discounts
Book Now

Your AI Wingman for your next interview

The most comprehensive bank Interview Answer Review tooling available online.

Cutting-edge AI technology meets personalized feedback. Improve your interview answers with insightful guidance provided by a model trained against more than a million human-labelled interview answers.
  • Company rubrics
  • Role-level optimisations
  • Trained on 1mil+ answers
Behavioral
4 years ago
Could you briefly outline your professional journey?
Design Verification EngineerEmbedded Engineer

Samsung Electronics

NEC

Benchmark Electronics

Get answer reviewed by AI
4 years ago
Technical KnowledgeEmbedded System Design
4 years ago
What, in your experience, leads to a memory leak and how do you propose to prevent such occurrences?
Embedded Engineer

Samsung Electronics

Magna International

Arm

Get answer reviewed by AI
4 years ago
Embedded CodingTechnical Knowledge
4 years ago
What are the key functions of a locator in the context of embedded systems?
Embedded Engineer

Samsung Electronics

Xilinx Logo

Xilinx

Valeo Logo

Valeo

Get answer reviewed by AI
4 years ago
Algorithms
4 years ago
What are Perl's key advantages over its scripting language counterparts?
Design Verification Engineer

Samsung Electronics

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

Get answer reviewed by AI
4 years ago
Technical
4 years ago
Please provide an overview of the UVM RAL model and its necessity.
Design Verification Engineer

Samsung Electronics

Sumitomo Electric Logo

Sumitomo Electric

KLA Logo

KLA

Get answer reviewed by AI
4 years ago
Circuits
4 years ago
How do you plan to assess the depth of a FIFO?
Design Verification Engineer

Samsung Electronics

KLA Logo

KLA

BMW Group Logo

BMW Group

Get answer reviewed by AI
4 years ago
Technical
4 years ago
Can you outline the key aspects of a Testbench?
Design Verification Engineer

Samsung Electronics

Broadcom Logo

Broadcom

Philips Healthcare Logo

Philips Healthcare

Get answer reviewed by AI
4 years ago
Verilog Coding
4 years ago
Can you demonstrate how to craft an SVA in System Verilog that blocks memory access during power-on-reset?
Design Verification Engineer

Samsung Electronics

Xilinx Logo

Xilinx

Ericsson Logo

Ericsson

Get answer reviewed by AI
4 years ago
Technical
4 years ago
What makes the create method more suitable than the new constructor in UVM?
Design Verification Engineer

Samsung Electronics

Thales Logo

Thales

Nuvoton Technology Logo

Nuvoton Technology

Get answer reviewed by AI
4 years ago
Behavioral
4 years ago
Would you be able to share an experience where you went above and beyond for a project?
Design Verification EngineerEmbedded Engineer

Samsung Electronics

Lockheed Martin Logo

Lockheed Martin

Sumitomo Electric Logo

Sumitomo Electric

Get answer reviewed by AI
4 years ago

Question of the week

We'll send you a weekly question to practice for:

Showing 241 to 250 of 277 results

Previous2324252627Next

*All interview questions are submitted by recent Samsung Electronics candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Samsung Electronics employees.

  • Company
  • FAQs
  • Contact Us
  • Become An Expert
  • Services
  • Practice Interviews
  • Interview Guides
  • Interview Questions
  • Watch Recorded Interviews
  • Gift sessions
  • AI Interview
  • Social
  • Twitter
  • Facebook
  • LinkedIn
  • YouTube
  • Legal
  • Terms & Conditions
  • Privacy Policy
  • Illustrations by Storyset

© 2025 Prepfully. All rights reserved.

Prepfully logo

Please log in to view more questions.

Not a member yet? Sign up for free.