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Technical
a year ago
Please outline your method for IP verification. In cases where a new IP is added to your design, how do you validate it?
Design Verification Engineer

Microsoft

Palo Alto Networks

Amazon

SPEC understanding

Verification plan

Test planning

Testcases development (Random constrained and directed tests)

Assertion based verification 

Achieving Code coverage 100% 

Achieving Functional coverage 100%

Formal verification if needed 

final sign off if everything above is achieved


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a year ago
DesignCircuits
a year ago
What’s your plan for engineering a multi-bit FIFO circuit?
Design Verification Engineer

Google

Safran

Northrop Grumman

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a year ago
Behavioral
a year ago
Please share a past decision that didn't lead to success. What valuable lessons did you learn?
Design Verification EngineerEmbedded Engineer

Amazon

Google

Amgen Logo

Amgen

In one of my previous roles, I was tasked with debugging a critical issue in a design verification testbench. The problem seemed minor initially, so I chose to focus on a quick fix without thoroughly analyzing the root cause. While the testbench passed some initial runs, the issue resurfaced in a different part of the design during integration, causing delays in the overall verification process.


This experience taught me the importance of addressing issues systematically rather than opting for quick fixes. Now, whenever I encounter a problem, I take the time to dig into the root cause, even if it requires additional effort upfront. This approach has significantly improved the reliability of my contributions and prevented similar issues from recurring in subsequent projects

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a year ago
Technical
a year ago
In what ways is UVM beneficial for design verification?
Design Verification Engineer

Microsoft

Keysight Technologies Logo

Keysight Technologies

Xilinx Logo

Xilinx

1. Reusability

2. Maintainability

3. Standard methodology makes it easier to understand the data flow for new members

4. Built-in code helps to do things in a standard way and also avoids minor mistakes

5. Scalability increases

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a year ago
Behavioral
a year ago
How would you address the issue of a colleague frequently being late to scheduled gatherings?
Design Verification EngineerEmbedded Engineer

Google

Apple Logo

Apple

Cirrus Logic Logo

Cirrus Logic

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a year ago
Technical
a year ago
How would you differentiate between a fork and a join when it comes to multithreaded systems?
Design Verification Engineer
KLA Logo

KLA

Philips Healthcare Logo

Philips Healthcare

Cruise Logo

Cruise

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a year ago
Behavioral
a year ago
I'd like to hear about a decision you made that wasn't favored by others.
Design Verification EngineerEmbedded Engineer
Meta Logo

Meta

Arm Logo

Arm

Philips Healthcare Logo

Philips Healthcare

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a year ago
Design
a year ago
What's your interpretation of the synthesis flow in the context of VLSI design?
Design Verification Engineer

Google

Boston Scientific Logo

Boston Scientific

Synopsys Logo

Synopsys

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a year ago
Technical
a year ago
Can you elucidate what is meant by an 'event' in Verilog?
Design Verification Engineer

Amazon

Micron Technology Logo

Micron Technology

Taiwan Semiconductor Logo

Taiwan Semiconductor

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a year ago
Verilog Coding
a year ago
Can you delineate the distinctions between RTL and behavioral coding in Verilog?
Design Verification Engineer
Prysmian Group Logo

Prysmian Group

Honeywell Logo

Honeywell

Bombardier Logo

Bombardier

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a year ago

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Amazon logo

Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

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Behavioral

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