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Circuits
2 years ago
Can you illustrate the IDD curve for an inverter during a transition from OFF to ON state?
Design Verification Engineer

Amazon

Yokogawa Electric

Nuro

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2 years ago
Circuits
2 years ago
What's your approach to building a NAND gate with only 2:1 MUXes?
Design Verification Engineer

Microsoft

Rolls-Royce Aerospace

GlobalFoundries

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2 years ago
Verilog Coding
2 years ago
What are some commonly used Verilog constructs in verification environment development?
Design Verification Engineer
Microchip Technology Logo

Microchip Technology

Rolls-Royce Aerospace

Kingston Technology Logo

Kingston Technology

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2 years ago
Design
2 years ago
Can you draft a design for a 3 bit shift register in verilog RTL?
Design Verification Engineer
Palo Alto Networks Logo

Palo Alto Networks

Hewlett Packard Logo

Hewlett Packard

NETGEAR Logo

NETGEAR

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2 years ago
Circuits
2 years ago
Can you explain the voltage changes in two parallel capacitors with different charges when the connecting transistor turns on?
Design Verification Engineer
Google Logo

Google

Arista Networks Logo

Arista Networks

Dialog Semiconductor Logo

Dialog Semiconductor

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2 years ago
Technical
2 years ago
In your own words, how would you explain clock domain crossing and its challenges?
Design Verification Engineer
Cisco Logo

Cisco

Northrop Grumman Logo

Northrop Grumman

Western Digital Logo

Western Digital

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2 years ago
Technical
2 years ago
Could you describe a scenario where employing a virtual interface in SystemVerilog enhanced design verification?
Design Verification Engineer
Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Novartis Logo

Novartis

GlobalFoundries

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2 years ago
Computer Architecture
2 years ago
What do you understand by VLSI and can you name some of its main applications?
Design Verification Engineer
Garmin Logo

Garmin

Microchip Technology Logo

Microchip Technology

Kingston Technology Logo

Kingston Technology

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2 years ago
Verilog Coding
2 years ago
What happens to the value of 'out' if 'a' is “1’bx”?
Design Verification Engineer
Meta Logo

Meta

Palo Alto Networks Logo

Palo Alto Networks

Raymarine Logo

Raymarine

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2 years ago
Behavioral
2 years ago
Recall a moment when you were pressed for time to meet a deadline. How did you cope?
Design Verification Engineer
NEC Logo

NEC

Aurora Logo

Aurora

Oracle Logo

Oracle

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2 years ago

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Amazon logo

Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

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Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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