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Verilog Coding
2 years ago
Please craft a Verilog snippet to populate a 10x9 array with zeros at 0ns in an initial block.
Design Verification Engineer

Xiaomi

Beckman Coulter

Bombardier Transportation

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2 years ago
Circuits
2 years ago
When J and K inputs of a JK flip-flop are set to 0, and it's driven by a 10MHz square wave, what is the resulting output frequency?
Design Verification Engineer

GlobalFoundries

Western Digital

Alstom

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2 years ago
Technical
2 years ago
How does a single-channel DMA controller function? And in what way does it handle multiple channels and peripheral agents concurrently?
Design Verification Engineer

GlobalFoundries

Sony Logo

Sony

Marvell Logo

Marvell

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2 years ago
Behavioral
2 years ago
In the case of a team member regularly arriving late to meetings, what would your response be?
Design Verification EngineerEmbedded Engineer
Google Logo

Google

Apple Logo

Apple

Hewlett Packard Logo

Hewlett Packard

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2 years ago
Chip Design
2 years ago
Design a range of counters, including a specialized mod-15 counter that leaves out 0, 3, 4, 8, and 5.
Design Verification Engineer
Nuvoton Technology Logo

Nuvoton Technology

Nuro Logo

Nuro

GlobalFoundries

module mod_15_counter (

  input wire clk,      // Clock signal

  input wire reset_n,  // Active low reset

  output reg [3:0] count // 4-bit counter output

);

  

  // Combinational logic to determine the next valid state

  always @(posedge clk or negedge reset_n) begin

    if (!reset_n)

      count <= 1;  // Start from 1 when reset is active

    else begin

      case (count)

        1: count <= 2;

        2: count <= 6;

        6: count <= 7;

        7: count <= 9;

        9: count <= 10;

        10: count <= 11;

        11: count <= 12;

        12: count <= 13;

        13: count <= 14;

        14: count <= 15;

        15: count <= 1; // Wrap around to 1 after 15

        default: count <= 1;  // Default case to start from 1

      endcase

    end

  end


endmodule


module tb_mod_15_counter;


  reg clk;

  reg reset_n;

  wire [3:0] count;

  

  // Instantiate the mod-15 counter

  mod_15_counter uut (

    .clk(clk),

    .reset_n(reset_n),

    .count(count)

  );

  

  // Clock generation

  always #5 clk = ~clk;  // Clock period of 10 time units


  initial begin

    // Initialize signals

    clk = 0;

    reset_n = 0;

    

    // Apply reset

    #10 reset_n = 1;

    

    // Let the simulation run for 200 time units

    #200 $stop;

  end

  

  // Monitor the output

  initial begin

    $monitor("Time: %0d, count: %0d", $time, count);

  end


endmodule




 

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2 years ago
Algorithms
2 years ago
How do you approach the task of converting a hexadecimal number into binary?
Design Verification Engineer
Emerson Electric Logo

Emerson Electric

ASML Logo

ASML

Belkin Logo

Belkin

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2 years ago
Circuits
2 years ago
How would you describe a shift register and its functioning, supported by a circuit diagram?
Design Verification Engineer
Apple Logo

Apple

Amazon Logo

Amazon

OMRON Logo

OMRON

nand gate truth table 

a  b  y 

0  0  1

0  1  0

1  0  0

1  1  0

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2 years ago
Technical
2 years ago
Can you explain the purpose of the factory in UVM?
Design Verification Engineer
Meta Logo

Meta

Palo Alto Networks Logo

Palo Alto Networks

Abbott Laboratories Logo

Abbott Laboratories

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2 years ago
Technical
2 years ago
What contrasting features do RISC and CISC architectures possess?
Design Verification Engineer
Verizon Logo

Verizon

SpaceX Logo

SpaceX

TP-Link Logo

TP-Link

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2 years ago
Behavioral
2 years ago
What has spurred your current pursuit of employment?
Design Verification EngineerEmbedded Engineer
Microsoft Logo

Microsoft

Mercedes-Benz Logo

Mercedes-Benz

Razer Logo

Razer

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2 years ago

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Amazon logo

Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

Prepare for Behavioral interview at Google

Behavioral
Meta logo

Meta

Design Verification Engineer

Prepare for Behavioral interview at Meta

Behavioral

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