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Verilog Coding

2 years ago

Could you craft an SVA in System Verilog to confirm the sequence of a signal going from 0 to 1 before another drops from 1 to 0?

Design Verification Engineer

Thermo Fisher Scientific

Kawasaki Heavy Industries

Philips Healthcare

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2 years ago

Technical

2 years ago

Can you explain how blocking assignments differ from non-blocking assignments in Verilog?

Design Verification Engineer

ASML

Medtronic

Xilinx

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2 years ago

Verilog Coding

2 years ago

Can you construct HDL code for a FSM with states IDLE, READ, WRITE, transitioning on "op" and reverting to IDLE every 4 clock cycles?

Design Verification Engineer

Juniper Networks

NXP Semiconductors

NVIDIA

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2 years ago

Behavioral

2 years ago

Please discuss a notable failure in your career and the lessons it taught you.

Design Verification Engineer

Acer

Safran

IBM

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2 years ago

Behavioral

2 years ago

What has been the most significant challenge you've faced professionally?

Design Verification EngineerEmbedded Engineer

Lam Research

Thermo Fisher Scientific

Juul Labs

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2 years ago

Technical

2 years ago

What benefits does the create method offer over the new constructor in UVM?

Design Verification Engineer

Palo Alto Networks

Google

Fujitsu

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2 years ago

Design

2 years ago

Could you describe the violations that are often faced and how you work to avoid them?

Design Verification Engineer

Realtek

Mentor Graphics

Sharp

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2 years ago

Technical

2 years ago

In your workflow, how do you conduct IP verification? Suppose a new IP is integrated into your design, how do you verify its functionality?

Design Verification Engineer

Microsoft

Palo Alto Networks

Amazon

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2 years ago

Technical

2 years ago

What's your understanding of cache coherence protocols and their significance?

Design Verification Engineer

Apple

Infineon

Cruise

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2 years ago

Technical

2 years ago

Please provide an instance of a coverage point in your verification setup and your approach to achieving coverage.

Design Verification Engineer

Palo Alto Networks

Sumitomo Electric

Prysmian Group

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2 years ago

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Showing 13531 to 13540 of 32012 results

^*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.