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Circuits
3 years ago
Can you outline the various phases in UVM and explain how they are initiated?
Design Verification Engineer

Philips Healthcare

Apple

Palo Alto Networks

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3 years ago
Design
3 years ago
I'm interested in your method for designing state machines and sequence detectors for various applications. What are the important design aspects and optimization techniques?
Design Verification Engineer

Philips Healthcare

Palo Alto Networks

Thales

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3 years ago
Algorithms
3 years ago
Could you demonstrate creating two unique arrays, each containing 10 different elements?
Design Verification Engineer

Philips Healthcare

Google Logo

Google

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Autodesk

class abc;

rand int a[10];

rand int b[10];

constraint c1{foreach(a[i])  a[i] inside{[1:100]};

                      unique{a[i]}; }

constraint c2{foreach(b[i])  b[i] inside{[1:100]};

                      b[i]!=a[i];}

function void post_randomize();

$display("a=%d, b=%d", a, b);

endfunction

endclass

module tb;

abc num=new();

initial begin

num.randomize();

end

endmodule

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3 years ago
Verilog Coding
3 years ago
What results in 'out' when 'a' is set to “1’bx”?
Design Verification Engineer

Philips Healthcare

Meta Logo

Meta

Palo Alto Networks

Simple if a is directly assigned then the value of out is 1'bx or undefined value like this out=a; and the out is either wire or reg data type

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3 years ago
Circuits
3 years ago
In what way would you establish the depth of a FIFO?
Design Verification Engineer

Philips Healthcare

KLA Logo

KLA

BMW Group Logo

BMW Group

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3 years ago
Technical
3 years ago
Please explain the contrast between the get_next_item() and get() methods in the UVM driver class.
Design Verification Engineer

Philips Healthcare

Meta Logo

Meta

ABB Logo

ABB

get_next_item is used when communicating with the sequence. it unblocks the start_item(req) in the sequence. 

get is used for communication with other components that are connected with the driver via tlm fifo port

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3 years ago
Design
3 years ago
In VLSI design, how would you differentiate between delay and slew rate?
Design Verification Engineer

Philips Healthcare

Apple

Amazon Logo

Amazon

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3 years ago
Verilog Coding
3 years ago
Design Verilog code that facilitates the detection of positive and negative edges.
Design Verification Engineer

Philips Healthcare

AT&T Logo

AT&T

Medtronic Logo

Medtronic

module edge_detector(input clk, input signal, output edge);

    always @(posedge clk) begin

    fork

@(poedge signal) edge <=1;

join_none

fork

@(negedge signal) edge <=0;

join_non

    end

endmodule

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3 years ago
Technical
3 years ago
What separates SystemVerilog assertions from UVM assertions in your perspective?
Design Verification Engineer

Philips Healthcare

Microsoft Logo

Microsoft

Toshiba Logo

Toshiba

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3 years ago
Technical
3 years ago
How are the 'new' and 'create' methods in UVM distinct from each other?
Design Verification Engineer

Philips Healthcare

Meta Logo

Meta

Fujitsu Logo

Fujitsu

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3 years ago

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*All interview questions are submitted by recent Philips Healthcare candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Philips Healthcare employees.

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