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Design
7 months ago
What are the specific pins and their quantity in a TAP interface for a JTAG boundary scan?
Design Verification Engineer

Palo Alto Networks

Belkin

Hitachi

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7 months ago
Technical
7 months ago
Could you explain what setup time and hold time are, and how violations of these times occur, along with strategies to minimize such violations?
Design Verification Engineer

Palo Alto Networks

Embraer Logo

Embraer

Amazon Logo

Amazon

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7 months ago
Technical
7 months ago
Can you explain the functioning of the SD Card model from your project and the hurdles you overcame?
Design Verification Engineer

Palo Alto Networks

Fujitsu Logo

Fujitsu

Novartis Logo

Novartis

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7 months ago
Technical
8 months ago
What makes a positive edge trigger different from a negative edge trigger in Verilog?
Design Verification Engineer

Palo Alto Networks

Boston Scientific Logo

Boston Scientific

Teradyne Logo

Teradyne

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8 months ago
Technical
8 months ago
What kinds of timing violations are typically seen in RTL designs?
Design Verification Engineer

Palo Alto Networks

Qualcomm Logo

Qualcomm

Acer Logo

Acer

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8 months ago
Algorithms
9 months ago
Could you discuss the strengths of Perl against other scripting languages?
Design Verification Engineer

Palo Alto Networks

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

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9 months ago
Technical
9 months ago
What are the fundamentals of a cache and its operational methodology?
Design Verification Engineer

Palo Alto Networks

Garmin Logo

Garmin

Keysight Technologies Logo

Keysight Technologies

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9 months ago
Design
9 months ago
How would you go about designing a 3 bit shift register in verilog RTL?
Design Verification Engineer

Palo Alto Networks

NETGEAR Logo

NETGEAR

Infineon Logo

Infineon

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9 months ago
Technical
10 months ago
Can you explain the advantages of using create method instead of a new constructor in UVM?
Design Verification Engineer

Palo Alto Networks

Thales Logo

Thales

Nuvoton Technology Logo

Nuvoton Technology

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10 months ago
Technical
10 months ago
How has a virtual interface in SystemVerilog been helpful in any of your design verification projects?
Design Verification Engineer

Palo Alto Networks

Novartis Logo

Novartis

GlobalFoundries Logo

GlobalFoundries

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10 months ago

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