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property check_setup_hold;

  logic clk, rst;

  logic data, data_en;  // Input data and its enable signal

  @(posedge clk)

  disable iff (rst) 

  $rose(data_en) |-> 

      ##[Setup_Time:Setup_Time] data_stable  ##1 

      data_stable throughout $fell(data_en) ##[Hold_Time:Hold_Time]; 

endproperty 

sequence data_stable;

  (data == 1'b0) || (data == 1'b1); 

endsequence

assert property (check_setup_hold(clk, rst, data, data_en));

I’ve spent the last few years working in fast-paced startup environments, building financial infrastructure systems—things like secure transaction pipelines, internal tooling, and real-time data processing. It was a great experience that gave me strong ownership over the entire engineering lifecycle, from design to deployment.

Now, I’m looking to take the next step by joining a larger-scale engineering organization like Amazon, where I can work on highly reliable, distributed systems with broader impact. I’m especially drawn to Amazon’s engineering standards, mentorship opportunities, and the chance to contribute to systems that operate at global scale.

Ultimately, I’m motivated by solving hard problems with high stakes, and I want to grow as a builder by learning from experienced engineers and contributing to long-term infrastructure projects that matter.

In a pulse generator circuit using a 2-input NAND gate and inverters with propagation delays, the output pulse timing can be understood through the following steps:

Understanding NAND Gate Behavior:

A 2-input NAND gate outputs a LOW (0) when both inputs are HIGH (1); otherwise, it outputs HIGH (1).

Input Timing Diagram:

Let's denote the two inputs to the NAND gate as 

𝐴

A and 

𝐵

B.

Assume 

𝐴

A and 

𝐵

B have some input pulse timings (HIGH and LOW transitions) over time.

Propagation Delay of Inverters:

Inverters introduce a small delay in propagating the input signal to their output. This delay could be denoted as 

𝜏

τ (tau).

Output Timing Diagram:

Initially, when both inputs 

𝐴

A and 

𝐵

B are LOW (0), the NAND gate output will be HIGH (1).

When one of the inputs (say 

𝐴

A) transitions from LOW to HIGH (0 to 1):

Due to the propagation delay 

𝜏

τ, the output of the corresponding inverter connected to 

𝐴

A will change with a delay.

This delay causes a brief moment where the NAND gate sees one input (from 

𝐵

B) as HIGH and the other (from 

𝐴

A) as still LOW (since 

𝐴

A is transitioning).

Therefore, the NAND gate output will momentarily go LOW (0) during this transition period.

As 

𝐴

A completes its transition to HIGH, the output of the NAND gate will go HIGH (1) again.

Output Pulse Generation:

The circuit can be designed such that the momentary LOW (0) output from the NAND gate, caused by the input transition of 

𝐴

A, generates a pulse.

This pulse width is determined by the propagation delay 

𝜏

τ of the inverters.

Subsequent transitions of 

𝐵

B or 

𝐴

A will create additional pulses, depending on their timing relative to each other and considering the propagation delays.

Summary:

The output of the pulse generator circuit will reflect the timing of the input transitions, modified by the propagation delays of the inverters.

Each transition of the inputs 

𝐴

A and 

𝐵

B can potentially generate a brief pulse at the output of the NAND gate, depending on their timing and the circuit design.

Initially i will think of basic scenarios possible by understanding the design documents. For example if its a memory to be verified i will think about below basic tests:

1. Reset

2. Random read

3. Random write

4. Read and write for different address at the same time

Post these tests i will think of directed tests for better corner cases:

1. Odd address write/read

2. Even address write/read

3. Empty location read

4. Rewriting in the same location