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Technical
a year ago
What's your history with validation/prototype and synthesis in design projects? How do you tackle these aspects?
Design Verification Engineer

Meta

Juniper Networks

ABB

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a year ago
Technical
a year ago
What contrasting features do RISC and CISC architectures possess?
Design Verification Engineer

Meta

SpaceX

TP-Link

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a year ago
Verilog Coding
a year ago
How would you design an SVA in System Verilog to verify a signal switches from 0 to 1 prior to another signal's transition from 1 to 0?
Design Verification Engineer

Meta

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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a year ago
Technical
2 years ago
In Verilog, how do blocking assignments contrast with non-blocking ones?
Design Verification Engineer

Meta

Medtronic Logo

Medtronic

Xilinx Logo

Xilinx

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2 years ago
Technical
2 years ago
Could you explain the difference between positive edge triggering and negative edge triggering in Verilog?
Design Verification Engineer

Meta

Boston Scientific Logo

Boston Scientific

Teradyne Logo

Teradyne

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2 years ago
CircuitsDesign
2 years ago
In what manner would you develop a multi-bit FIFO circuit?
Design Verification Engineer

Meta

Northrop Grumman Logo

Northrop Grumman

Taiwan Semiconductor Logo

Taiwan Semiconductor

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2 years ago
Technical
2 years ago
Can you describe the functioning of a basic single-channel DMA controller? Also, how does it manage multiple channels and peripheral agents simultaneously?
Design Verification Engineer

Meta

Sony Logo

Sony

Marvell Logo

Marvell

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2 years ago
Technical
2 years ago
How do virtual functions function in OOP, and what sets them apart from regular member functions?
Design Verification Engineer

Meta

Varian Medical Systems Logo

Varian Medical Systems

Silicon Motion Logo

Silicon Motion

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2 years ago
Behavioral
2 years ago
What methods do you use to alter your communication style effectively?
Design Verification EngineerEmbedded Engineer

Meta

BAE Systems Logo

BAE Systems

Microchip Technology Logo

Microchip Technology

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2 years ago
Verilog Coding
2 years ago
How would you implement a module to calculate the dot product of two vectors of equal length?
Design Verification Engineer

Meta

Bombardier Logo

Bombardier

Apple Logo

Apple

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2 years ago

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*All interview questions are submitted by recent Meta Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Meta.

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