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In one of my previous roles, I was tasked with debugging a critical issue in a design verification testbench. The problem seemed minor initially, so I chose to focus on a quick fix without thoroughly analyzing the root cause. While the testbench passed some initial runs, the issue resurfaced in a different part of the design during integration, causing delays in the overall verification process.

This experience taught me the importance of addressing issues systematically rather than opting for quick fixes. Now, whenever I encounter a problem, I take the time to dig into the root cause, even if it requires additional effort upfront. This approach has significantly improved the reliability of my contributions and prevented similar issues from recurring in subsequent projects

module mod_15_counter (

  input wire clk,      // Clock signal

  input wire reset_n,  // Active low reset

  output reg [3:0] count // 4-bit counter output

);

  // Combinational logic to determine the next valid state

  always @(posedge clk or negedge reset_n) begin

    if (!reset_n)

      count <= 1;  // Start from 1 when reset is active

    else begin

      case (count)

        1: count <= 2;

        2: count <= 6;

        6: count <= 7;

        7: count <= 9;

        9: count <= 10;

        10: count <= 11;

        11: count <= 12;

        12: count <= 13;

        13: count <= 14;

        14: count <= 15;

        15: count <= 1; // Wrap around to 1 after 15

        default: count <= 1;  // Default case to start from 1

      endcase

    end

  end

endmodule

module tb_mod_15_counter;

  reg clk;

  reg reset_n;

  wire [3:0] count;

  // Instantiate the mod-15 counter

  mod_15_counter uut (

    .clk(clk),

    .reset_n(reset_n),

    .count(count)

  );

  // Clock generation

  always #5 clk = ~clk;  // Clock period of 10 time units

  initial begin

    // Initialize signals

    clk = 0;

    reset_n = 0;

    // Apply reset

    #10 reset_n = 1;

    // Let the simulation run for 200 time units

    #200 $stop;

  end

  // Monitor the output

  initial begin

    $monitor("Time: %0d, count: %0d", $time, count);

  end

endmodule

I’ve spent the last few years working in fast-paced startup environments, building financial infrastructure systems—things like secure transaction pipelines, internal tooling, and real-time data processing. It was a great experience that gave me strong ownership over the entire engineering lifecycle, from design to deployment.

Now, I’m looking to take the next step by joining a larger-scale engineering organization like Amazon, where I can work on highly reliable, distributed systems with broader impact. I’m especially drawn to Amazon’s engineering standards, mentorship opportunities, and the chance to contribute to systems that operate at global scale.

Ultimately, I’m motivated by solving hard problems with high stakes, and I want to grow as a builder by learning from experienced engineers and contributing to long-term infrastructure projects that matter.

Situation:

Success can be measured in different ways depending on the context—whether it’s a project milestone, team collaboration, or personal growth. For me, success is about achieving the intended goal while creating a lasting impact, whether that means delivering high-quality verification, improving efficiency, or mentoring others to grow.

Task:

One example that defines my success criteria was when I was responsible for closing the verification of a complex IP. The challenge was that I had limited resources—a team of mostly junior and mid-level engineers—and tight timelines. Success in this scenario wasn’t just about delivering verification but also ensuring that my team could ramp up and work independently.

Action:

To achieve this, I:

• Developed structured onboarding materials to accelerate the team's understanding of the testbench.

• Strategized task distribution to ensure each engineer had ownership of a small but impactful portion of the verification process.

• Created a collaborative debugging process, where team members could efficiently troubleshoot and escalate issues.

• Ensured verification coverage met the expected metrics while identifying and fixing key testbench gaps.

Result:

We successfully completed verification on time, identified critical testbench bugs, and delivered a well-documented framework that continues to benefit future teams. To me, this was a success because:

1. The technical objective (verification sign-off) was achieved.

2. The team grew and became self-sufficient, reducing dependency on senior engineers.

3. The long-term impact was positive, as the documentation and processes set up are still in use.

module fsm (

  input wire clk,         // Clock signal

  input wire reset_n,     // Active low reset

  input wire op,          // Operation signal: 0 for READ, 1 for WRITE

  output reg [1:0] state  // Current state of the FSM

);

  // Define states using parameters

  localparam [1:0] IDLE  = 2'b00,

                   READ  = 2'b01,

                   WRITE = 2'b10;

  reg [1:0] next_state;   // Next state logic

  reg [2:0] cycle_count;  // Counter for clock cycles (3-bit to count up to 4)

  // State transition logic (sequential logic)

  always @(posedge clk or negedge reset_n) begin

    if (!reset_n) begin

      state <= IDLE;           // Reset to IDLE state

      cycle_count <= 3'b000;   // Reset cycle counter

    end

    else begin

      state <= next_state;     // Update current state to next state

      if (state == READ || state == WRITE) begin

        cycle_count <= cycle_count + 1'b1;  // Increment counter in READ/WRITE

      end

      else begin

        cycle_count <= 3'b000;  // Reset counter in IDLE state

      end

    end

  end

  // Next state logic (combinational logic)

  always @(*) begin

    case (state)

      IDLE: begin

        if (op == 1'b0)

          next_state = READ;  // Go to READ state if op is 0

        else

          next_state = WRITE; // Go to WRITE state if op is 1

      end

      READ: begin

        if (cycle_count == 3'd3)

          next_state = IDLE;  // After 4 clock cycles, go back to IDLE

        else

          next_state = READ;  // Remain in READ state until 4 cycles

      end

      WRITE: begin

        if (cycle_count == 3'd3)

          next_state = IDLE;  // After 4 clock cycles, go back to IDLE

        else

          next_state = WRITE; // Remain in WRITE state until 4 cycles

      end

      default: next_state = IDLE;  // Default case to handle any invalid state

    endcase

  end

endmodule