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Design
3 years ago
In your view, what are the various adders used in VLSI design? How do you optimize these adders for different types of applications?
Design Verification Engineer
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Lenovo

National Instruments Logo

National Instruments

Emerson Electric Logo

Emerson Electric

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3 years ago
Chip Design
3 years ago
Craft counters suitable for various applications, such as a mod-15 counter excluding 0, 3, 4, 8, and 5.
Design Verification Engineer
Lenovo Logo

Lenovo

Nuro Logo

Nuro

GlobalFoundries Logo

GlobalFoundries

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3 years ago
Technical
3 years ago
What’s your strategy for using fork-join parallelism to boost computation speeds?
Design Verification Engineer
Lenovo Logo

Lenovo

Dell Technologies Logo

Dell Technologies

OMRON Logo

OMRON

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3 years ago
Verilog Coding
3 years ago
How would you go about implementing a binary-to-thermometer decoder in Verilog?
Design Verification Engineer
Lenovo Logo

Lenovo

Bosch Logo

Bosch

Fujikura Logo

Fujikura

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3 years ago
Algorithms
3 years ago
What benefits does Perl offer that are not found in other scripting languages?
Design Verification Engineer
Lenovo Logo

Lenovo

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

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3 years ago
Technical
3 years ago
Can you identify the radix in the equation 121(r) = 144(8)?
Design Verification Engineer
Lenovo Logo

Lenovo

Silicon Motion Logo

Silicon Motion

AIRBUS Logo

AIRBUS

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3 years ago
Circuits
3 years ago
What are the key differences between positive and negative edge-triggered flip-flops?
Design Verification Engineer
Lenovo Logo

Lenovo

Xilinx Logo

Xilinx

Peloton Logo

Peloton

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3 years ago
Circuits
3 years ago
How do the voltages of two capacitors, charged differently and connected in parallel by a transistor, behave when the transistor is switched on?
Design Verification Engineer
Lenovo Logo

Lenovo

Dialog Semiconductor Logo

Dialog Semiconductor

Kingston Technology Logo

Kingston Technology

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3 years ago
Behavioral
3 years ago
What methods have you found effective in gaining your team's trust?
Design Verification EngineerEmbedded Engineer
Lenovo Logo

Lenovo

GlobalFoundries Logo

GlobalFoundries

Fujitsu Logo

Fujitsu

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3 years ago
Verilog Coding
3 years ago
Could you demonstrate writing HDL for a FSM having IDLE, READ, and WRITE states, with transitions triggered by "op" and a 4-clock-cycle reset to IDLE?
Design Verification Engineer
Lenovo Logo

Lenovo

NXP Semiconductors Logo

NXP Semiconductors

NVIDIA Logo

NVIDIA

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3 years ago

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*All interview questions are submitted by recent Lenovo Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Lenovo.

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