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Technical
a year ago
What distinguishes the # directive from the $timeformat directive in Verilog?
Design Verification Engineer

GE Aviation

Aurora

General Electric

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a year ago
Behavioral
2 years ago
Can you describe a time you were given tough feedback and how you managed it?
Design Verification EngineerEmbedded Engineer

GE Aviation

Canon

Cisco

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2 years ago
Technical
2 years ago
Can you compare the get_next_item() and get() methods in the UVM driver class?
Design Verification Engineer

GE Aviation

ABB Logo

ABB

Dell Logo

Dell

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2 years ago
Algorithms
2 years ago
In what ways is the Tomasulo Algorithm more effective than other scheduling algorithms? Have you used it in your projects? Can you give an example of its implementation and hazard mitigation?
Design Verification Engineer

GE Aviation

Cisco Systems Logo

Cisco Systems

Bosch Logo

Bosch

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2 years ago
Behavioral
2 years ago
What insights did you gain from a substantial failure at work?
Design Verification Engineer

GE Aviation

Safran Logo

Safran

IBM Logo

IBM

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2 years ago
Technical
2 years ago
Which aspect of Verilog is used for simulation time customization?
Design Verification Engineer

GE Aviation

Skyworks Solutions Logo

Skyworks Solutions

Triumph Motorcycles Logo

Triumph Motorcycles

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2 years ago
Behavioral
2 years ago
Narrate an experience of helping a team member in an area outside your expertise. What was the experience like?
Design Verification EngineerEmbedded Engineer

GE Aviation

Agilent Technologies Logo

Agilent Technologies

Raymarine Logo

Raymarine

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2 years ago
Technical
2 years ago
In UVM, what methods are used to ensure verification is both reusable and scalable?
Design Verification Engineer

GE Aviation

Mayo Clinic Logo

Mayo Clinic

Bombardier Logo

Bombardier

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2 years ago
Technical
2 years ago
In your view, how do formal verification and simulation-based verification differ?
Design Verification Engineer

GE Aviation

LG Electronics Logo

LG Electronics

Infineon Logo

Infineon

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2 years ago
Verilog Coding
2 years ago
How do you design an SVA in System Verilog to inhibit transaction initiation during a reset signal's activity?
Design Verification Engineer

GE Aviation

ASUS Logo

ASUS

NVIDIA Logo

NVIDIA

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2 years ago

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