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Circuits

2 years ago

When J and K inputs of a JK flip-flop are set to 0, and it's driven by a 10MHz square wave, what is the resulting output frequency?

Design Verification Engineer

Dell

Western Digital

Alstom

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2 years ago

Technical

2 years ago

How would you structure a test plan for a design verification project?

Design Verification Engineer

Dell

Yamaha Motor Corporation

AIRBUS

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2 years ago

Technical

2 years ago

In what ways are code coverage and functional coverage distinct from each other?

Design Verification Engineer

Dell

Amazon

Siemens

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2 years ago

Design

2 years ago

In designing routing algorithms for a multi-port/multi-speed switch/router, how would you ensure equal bandwidth sharing?

Design Verification Engineer

Dell

Northrop Grumman

STMicroelectronics

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2 years ago

Technical

2 years ago

In your own words, what does metastability mean?

Design Verification Engineer

Dell

Nokia

Nuvoton Technology

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2 years ago

Design

2 years ago

What types of assertions are critical for a FIFO design, and which conditions would you prioritize for validation?

Design Verification Engineer

Dell

Philips

ON Semiconductor

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2 years ago

Verilog Coding

2 years ago

How do you interpret the statement "wire #10 a = b & c" in context?

Design Verification Engineer

Dell

Fujikura

BAE Systems

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2 years ago

Verilog Coding

2 years ago

Describe how rand differs from randc in SystemVerilog, providing an example for each.

Design Verification Engineer

Dell

STMicroelectronics

Panasonic

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2 years ago

Circuits

2 years ago

In what way does a Linear Feedback Shift Register (LFSR) function?

Design Verification Engineer

Dell

Emerson Electric

ABB

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2 years ago

Technical

2 years ago

Can you distinguish between a flip flop and a latch?

Design Verification Engineer

Dell

Polaris Industries

Honeywell

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2 years ago

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