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Technical

4 months ago

In RTL designs, what are the potential timing violations that can arise?

Design Verification Engineer

Cisco

GlobalFoundries

Yokogawa Electric

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4 months ago

Technical

5 months ago

What separates the get_next_item() method from the get() method in UVM's driver class?

Design Verification Engineer

Cisco

Ericsson

Waymo

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5 months ago

Design

5 months ago

Can you elaborate on the importance of parasitic resistance in VLSI design?

Design Verification Engineer

Cisco

Huawei

Marvell

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5 months ago

Design

5 months ago

How would you define Floorplanning within the context of VLSI design?

Design Verification Engineer

Cisco Systems

Cisco

Ducati

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5 months ago

Technical

5 months ago

Can you outline what an assertion in SystemVerilog is and its implementation in design verification?

Design Verification Engineer

Cisco

AT&T

Mayo Clinic

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5 months ago

Behavioral

5 months ago

Discuss a situation where meeting a deadline was challenging for you.

Design Verification EngineerEmbedded Engineer

Cisco

NETGEAR

Tektronix

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5 months ago

Chip Design

6 months ago

Could you illustrate how to engineer a D flip-flop utilizing a multiplexer?

Design Verification Engineer

Cisco

Harley-Davidson

Prysmian Group

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6 months ago

Circuits

6 months ago

How would you describe a shift register and its functioning, supported by a circuit diagram?

Design Verification Engineer

Cisco

Oppo

ByteDance

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6 months ago

Behavioral

6 months ago

Think of an instance where you had to get someone on board with your idea. How did you go about it?

Design Verification EngineerEmbedded Engineer

Cisco

RS Components

STMicroelectronics

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6 months ago

Design

6 months ago

What typical violations do you encounter and what are your methods to prevent them?

Design Verification Engineer

Cisco Systems

Cisco

Micron Technology

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6 months ago

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^*All interview questions are submitted by recent Cisco Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Cisco.

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