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Technical

4 years ago

Could you describe your experience working with UVM and System Verilog?

Design Verification Engineer

Agilent Technologies

Triumph Motorcycles

Huawei

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4 years ago

Behavioral

4 years ago

What steps would you take if a peer consistently arrives late to a recurring meeting?

Embedded EngineerDesign Verification Engineer

Agilent Technologies

Philips

Synopsys

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4 years ago

Behavioral

4 years ago

Why should we consider you the top candidate for the Embedded Engineer position?

Embedded Engineer

Agilent Technologies

Magneti Marelli

Kyocera

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4 years ago

Embedded CodingTechnical Knowledge

4 years ago

How do recursive functions enhance functionality, and what is the outcome of declaring them as inline?

Embedded Engineer

Agilent Technologies

Schneider Electric

Applied Materials

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4 years ago

Technical

4 years ago

In terms of digital design, what are setup time and hold time? Can you discuss how violations of these occur and suggest methods to minimize them?

Design Verification Engineer

Agilent Technologies

Applied Materials

Safran

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4 years ago

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^*All interview questions are submitted by recent Agilent Technologies candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Agilent Technologies employees.