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Verilog Coding
2 years ago
How do you plan to execute the implementation of a 32-word 2R1W register file with programmable bitwidth?
Design Verification Engineer
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Agilent Technologies

Sumitomo Electric Logo

Sumitomo Electric

Waymo Logo

Waymo

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2 years ago
Technical
2 years ago
In System Verilog, how are reg, logic, and wire datatypes distinct from each other?
Design Verification Engineer
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Agilent Technologies

Johnson Controls Logo

Johnson Controls

MediaTek Logo

MediaTek

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2 years ago
Technical
2 years ago
Could you share an example of a coverage point from your verification environment and explain how you ensured coverage?
Design Verification Engineer
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Agilent Technologies

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

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2 years ago
Design
2 years ago
In your understanding, how do single and multi-port SRAM/DRAM memories operate? What are your approaches to ensuring memory is used efficiently and access time is kept to a minimum?
Design Verification Engineer
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Agilent Technologies

Harley-Davidson Logo

Harley-Davidson

ASUS Logo

ASUS

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2 years ago
Circuits
2 years ago
Using the write(addr, data) and read(addr, &data) APIs only, can you explain your method to identify a shorted internal signal in a device?
Design Verification Engineer
Agilent Technologies Logo

Agilent Technologies

Legrand Logo

Legrand

Applied Materials Logo

Applied Materials

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2 years ago
Design
2 years ago
What strategies would you employ to develop routing algorithms for a switch/router with various ports and speeds, aiming for balanced bandwidth sharing?
Design Verification Engineer
Agilent Technologies Logo

Agilent Technologies

Northrop Grumman Logo

Northrop Grumman

STMicroelectronics Logo

STMicroelectronics

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2 years ago
Technical
2 years ago
How do you intend to apply fork-join parallelism to improve computational efficiency?
Design Verification Engineer
Agilent Technologies Logo

Agilent Technologies

Dell Technologies Logo

Dell Technologies

OMRON Logo

OMRON

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2 years ago
Technical
2 years ago
What are the reasons for using the create method rather than the new constructor in UVM?
Design Verification Engineer
Agilent Technologies Logo

Agilent Technologies

Thales Logo

Thales

Nuvoton Technology Logo

Nuvoton Technology

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2 years ago
Technical
2 years ago
In your own words, what does metastability mean?
Design Verification Engineer
Agilent Technologies Logo

Agilent Technologies

Nokia Logo

Nokia

Nuvoton Technology Logo

Nuvoton Technology

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2 years ago
Verilog Coding
2 years ago
Can you describe the steps to implement a module for the dot product of two single-dimensional vectors?
Design Verification Engineer
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Agilent Technologies

Bombardier Logo

Bombardier

Apple Logo

Apple

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2 years ago

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*All interview questions are submitted by recent Agilent Technologies Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Agilent Technologies.

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