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Algorithms
3 years ago
Could you demonstrate writing a program that flips a linked list?
Design Verification Engineer

Abbott Laboratories

Intel

IBM

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3 years ago
Verilog Coding
3 years ago
Can you formulate SV code that results in unique random numbers?
Design Verification Engineer

Abbott Laboratories

Rohde & Schwarz

Palo Alto Networks

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3 years ago
Technical
3 years ago
Could you illustrate how a register table is used in the context of embedded systems?
Design Verification Engineer

Abbott Laboratories

Bosch Logo

Bosch

Verizon Logo

Verizon

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3 years ago
Behavioral
3 years ago
What's an example of a conflict you've encountered and how you dealt with it?
Design Verification EngineerEmbedded Engineer

Abbott Laboratories

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STMicroelectronics

Northrop Grumman Logo

Northrop Grumman

During one of our verification projects, we faced a challenge in defining the right test strategy for a new design block. I strongly advocated for merging an existing, previously verified block into a shared verification environment, believing it would improve efficiency and catch bugs with minimal effort. However, my teammate strongly advocated for a standalone block-level verification, arguing it would provide more deterministic coverage. This disagreement led to delays in testbench development and friction between us.

Recognizing the need for alignment, I initiated a structured discussion where we both presented our viewpoints with supporting data. I focused on ensuring we evaluated the trade-offs objectively rather than debating which approach was superior. After evaluating the pros and cons, I proposed a hybrid approach: conducting initial verification within the combined testbench for faster validation while simultaneously estimating the effort required for a standalone testbench. Once we mapped out our plans, we found that my approach led to a faster testbench setup, while his plan had overlaps in checker development. Recognizing this, we aligned on using the existing testbench while developing only the necessary new checkers. Later, we proposed building a dedicated block-level testbench to further improve coverage and verification confidence. This approach was well received by architects, designers, and management, as it balanced efficiency and thorough testing. It was a proud moment for me because it demonstrated the power of collaborative problem-solving, data-driven decision-making, and adaptability. This experience reinforced my belief that fostering open discussions, considering multiple perspectives, and focusing on practical solutions leads to stronger team synergy and better project outcomes.

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3 years ago
Behavioral
3 years ago
Narrate an instance that demanded a quick decision from you.
Design Verification EngineerEmbedded Engineer

Abbott Laboratories

Philips Logo

Philips

LG Electronics Logo

LG Electronics

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3 years ago
Technical
3 years ago
Could you differentiate between blocking and non-blocking assignments in Verilog?
Design Verification Engineer

Abbott Laboratories

Medtronic Logo

Medtronic

Xilinx Logo

Xilinx

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3 years ago
Verilog Coding
3 years ago
In System Verilog, how would you establish an assertion to maintain setup and hold time requirements for an input signal?
Design Verification Engineer

Abbott Laboratories

Mayo Clinic Logo

Mayo Clinic

Qualcomm Logo

Qualcomm

property check_setup_hold;

  logic clk, rst;

  logic data, data_en;  // Input data and its enable signal



  @(posedge clk)

  disable iff (rst) 

  $rose(data_en) |-> 

      ##[Setup_Time:Setup_Time] data_stable  ##1 

      data_stable throughout $fell(data_en) ##[Hold_Time:Hold_Time]; 

endproperty 



sequence data_stable;

  (data == 1'b0) || (data == 1'b1); 

endsequence



assert property (check_setup_hold(clk, rst, data, data_en));

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3 years ago
Technical
3 years ago
Could you detail the various timing violations that can manifest in RTL designs?
Design Verification Engineer

Abbott Laboratories

Qualcomm Logo

Qualcomm

Acer Logo

Acer

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3 years ago
Circuits
3 years ago
Can you construct the truth table representing a NAND gate's logic?
Design Verification Engineer

Abbott Laboratories

Xilinx Logo

Xilinx

Sumitomo Electric Logo

Sumitomo Electric

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3 years ago
Design
3 years ago
In what order do the stages in RTL design flow occur?
Design Verification Engineer

Abbott Laboratories

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Microsoft

Hitachi Logo

Hitachi

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3 years ago

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