NVIDIA Senior Design Verification Engineer

Technical Verification Leader with 13+ years of experience across SoC verification, GPU-centric architectures, low-power verification, emulation, post-silicon validation, XPROP, Gate Level Simulations, Coverage Closure and verification productivity. Currently working as a Senior Design Verification Lead, with hands-on ownership across verification planning, SystemVerilog/UVM development, constrained-random verification, assertions, coverage closure, debug, and automation. Applying AI-assisted engineering tools such as Cursor, Codex and Claude Code to improve verification productivity. I use AI-driven workflows to accelerate UVM/SystemVerilog code generation, refactoring, debug, automation script development, documentation, and repetitive verification tasks — helping teams move faster while maintaining engineering quality. I have led and contributed to end-to-end verification of complex SoC and GPU subsystems. Known for hands-on technical leadership, mentoring engineers, improving verification methodology, and driving productivity through automation, structured debug, and AI-assisted engineering practices.