RTL Design Engineer at Intel

I am an experienced RTL Design Engineer specializing in designing and implementing high-performance digital circuits. With a deep understanding of hardware description languages like Verilog and VHDL, I focus on creating efficient Register Transfer Level (RTL) code that meets stringent performance, power, and area requirements. My expertise spans across digital design, synthesis, and verification, ensuring seamless integration of designs into larger system-on-chip (SoC) architectures. I am proficient in using industry-standard tools for logic synthesis, simulation, and timing analysis, and I have a track record of contributing to the successful development of complex ASIC.