How did you go about constructing the testbench in one of your recent projects?

Question

Anonymous · Accepted Answer

I bult uvm testbench with top, test class, environment, scoreboard, agents,
drivers,monitor, sequences, sequence and tlm ports for connection. I bult
environment inside the top class and two agents inside environment and a
scoreboard. Bulit driver, monitor, sequences and sequences for each agent, made
connection between sequences and driver with tlm ports. Connected driver and
monitor to the virtual interface configured from top of test bench. Connected
two monitors to the scoreboard using uvm analysis port. Used virtual sequence
and sequencer for better arbitration of sequences. Sequence is the group of
transaction started on sequencer and sent to the driver using hand shaking
mechanism. Driver converts transactions into pin level signals which are the
inputs to the dut. Monitor collects the inputs which are drived to the dut and
sent to the reference model to generate expected output or results. Monitor
collects actual output from dut and sents to the scoreboard using analysis port.
In the scoreboard board the expected vs actual output are compared.

Anonymous · Answer

directory structure - comps, top, tests, seq, assert,run
Comps - env pkg, reg pkg, mem model, monitor and scoreboard
top - dut, dut_wrapper, top
tests - test base, vms.cfg, directed and random tests
Seqs- base seq - reset seq , clk driver seq , pwr mode transitions, memory
access, registers access seq
Assert - protocol checks, fsm checkers, ecc modelling and checkers

How did you go about constructing the testbench in one of your recent projects?

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