Could you detail the process of writing constraints in SystemVerilog?

Question

Anonymous · Accepted Answer

* To control the values that are getting assigned to the random variable on
   randomization we need      to define constraints.
 * Constraint provides  control on randomization.

class packet;
rand bit [3:0] addr;
constraint addr_range { addr > 5; }
endclass
module constr_blocks;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
pkt.randomize();
$display("	addr = %0d",pkt.addr);
end
end
endmodule

Could you detail the process of writing constraints in SystemVerilog?

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