What is the purpose of using a virtual interface in SV?

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Anonymous · Accepted Answer

An interface encompasses all the signals utilized in the design. A virtual
interface acts as a bridge between the SystemVerilog design and the testbench,
connecting the static design world with the dynamic testbench environment. Since
the DUT remains static and persists throughout the entire simulation, while
testbench components are dynamically created and destroyed, virtual interfaces
are employed to establish and maintain this connection seamlessly.

Anonymous · Answer

RTL and TB are connected through interface signals. Interface is nothing but
bundle of signals. While RTL is module based (i.e. static) and will ultimately
be made into hardware, testbench on the other side is class based and therefore
dynamic in nature. Virtual interface basically gives a pointer of actual
interface to testbench components.

What is the purpose of using a virtual interface in SV?

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