Can you describe what constitutes an event in Verilog?
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Answers
Anonymous
4 months ago
if you are talking about uvm_event. you need to first declare an uvm_event like uvm_event sent_e; then you could use this sent_e.trigger() sent_e.wait() to control the processes. Sometimes one process needs to wait for another process to be triggered first, and that is when you need to use an event.
Interview question asked to Design Verification Engineers interviewing at Schneider Electric, Arista Networks, Adobe and others: Can you describe what constitutes an event in Verilog?.