Can you explain how blocking assignments differ from non-blocking assignments in Verilog?
Design Verification Engineer
Palo Alto Networks
Qualcomm
ByteDance
Amgen
Corning
Emerson Electric
Answers
Anonymous
3 months ago
Blocking assignments perform combinational logic, propogating signals immediately. Non-blocking assignments perform sequential logic, propogating signals only upon trigger, one assignment at a time.
Interview question asked to Design Verification Engineers interviewing at ASML, Amgen, Palo Alto Networks and others: Can you explain how blocking assignments differ from non-blocking assignments in Verilog?.