Can you define an assertion in SystemVerilog and its role in design verification?
Design Verification Engineer
Palo Alto Networks
Microsoft
AT&T
Intel
Qualcomm
Samsung Electronics
Answers
Anonymous
3 months ago
Assertion defines the behavior of the design. In System Verilog, we use assertion with the keyword assert. We can assert the property and sequence
Interview question asked to Design Verification Engineers interviewing at Mayo Clinic, Rolls-Royce Aerospace, GE Aviation and others: Can you define an assertion in SystemVerilog and its role in design verification?.