Can you demonstrate how to construct a System Verilog Assertion that validates a signal's shift from 0 to 1 occurs before a different signal changes from 1 to 0?

Question

Anonymous · Accepted Answer

property transition_order;
    logic sig1, sig2;
    @(posedge clk) 
    disable iff (rst)  // Disable assertion during reset
    (sig1 == 0) ##1 (sig1 == 1) |-> ##[1:$] (sig2 == 1) ##1 (sig2 == 0); 
endproperty

assert property (transition_order(sig1, sig2));

Anonymous · Answer

Assume the second signal is sig b and first signal is sig a assert property
(@clk ) $fell(sig_b) |=> $rose(sig_a) else $display("error");

Anonymous · Answer

property a_before_b;

@(posedge clk)

// Once sig_b falls, sig_a must have risen earlier

$fell(sig_b) |-> $past($rose(sig_a), 1);

endproperty

assert property(a_before_b)

else $error("sig_a did not rise before sig_b fell");

Anonymous · Answer

bit a, b, rstn; // A rises first, then B falls at least one cycle later, active
low reset is rstn

property b_falls_after;

@(posedge clk) disable iff (!rstn) $rose(a) |-> ##[1:$] $fell(b);

endproperty

Anonymous · Answer

property transition_p @(posedge CLK) disable iff (!reset_n) {
$rose(b) |-> !$fell(a);
endproperty

Anonymous · Answer

write an assertion like assert( signal1 ==0 iff rose(signal2))

Can you demonstrate how to construct a System Verilog Assertion that validates a signal's shift from 0 to 1 occurs before a different signal changes from 1 to 0?

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