Verilog Coding
How would you design an SVA in System Verilog to verify a signal switches from 0 to 1 prior to another signal's transition from 1 to 0?
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Answers
Anonymous
4 months ago
property transition_order;
logic sig1, sig2;
@(posedge clk)
disable iff (rst) // Disable assertion during reset
(sig1 == 0) ##1 (sig1 == 1) |-> ##[1:$] (sig2 == 1) ##1 (sig2 == 0);
endproperty
assert property (transition_order(sig1, sig2));
Anonymous
5 months ago
write an assertion like assert( signal1 ==0 iff rose(signal2))
Interview question asked to Design Verification Engineers interviewing at Google, BAE Systems, Skyworks Solutions and others: How would you design an SVA in System Verilog to verify a signal switches from 0 to 1 prior to another signal's transition from 1 to 0?.