How would you design an SVA in System Verilog to verify a signal switches from 0 to 1 prior to another signal's transition from 1 to 0?

Interview question asked to Design Verification Engineers interviewing at Google, BAE Systems, Skyworks Solutions and others: How would you design an SVA in System Verilog to verify a signal switches from 0 to 1 prior to another signal's transition from 1 to 0?.