Can you demonstrate how to construct an SVA in System Verilog that enforces setup and hold time compliance for an input signal?

Question

Anonymous · Accepted Answer

property check_setup_hold;
  logic clk, rst;
  logic data, data_en;  // Input data and its enable signal

@(posedge clk)
  disable iff (rst) 
  $rose(data_en) |-> 
      ##[Setup_Time:Setup_Time] data_stable  ##1 
      data_stable throughout $fell(data_en) ##[Hold_Time:Hold_Time]; 
endproperty

sequence data_stable;
  (data == 1'b0) || (data == 1'b1); 
endsequence

assert property (check_setup_hold(clk, rst, data, data_en));

Anonymous · Answer

property setup_and_hold_check;
    @(posedge clk) 
    ##[0:$] (stable(data_in, tsetup)) |-> ##1 stable(data_in, thold);
endproperty

assert property (setup_and_hold_check)
    else $error("Setup or hold time violation detected on data_in signal.");

Anonymous · Answer

assert property @change(sig1); time t1= $time; |->$stable(sig1) && $rose(clk);
t1- $time == setup_time; |-> $stable(sig1) ; $time - t1+ setup_time >=
hold_time;

Can you demonstrate how to construct an SVA in System Verilog that enforces setup and hold time compliance for an input signal?

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