Verilog Coding

How would you compose an SVA in System Verilog to verify an input signal adheres to setup and hold time constraints?

Design Verification Engineer

Google

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Answers

Anonymous

8 months ago

property check_setup_hold;
  logic clk, rst;
  logic data, data_en;  // Input data and its enable signal

  @(posedge clk)
  disable iff (rst) 
  $rose(data_en) |-> 
      ##[Setup_Time:Setup_Time] data_stable  ##1 
      data_stable throughout $fell(data_en) ##[Hold_Time:Hold_Time]; 
endproperty 

sequence data_stable;
  (data == 1'b0) || (data == 1'b1); 
endsequence

assert property (check_setup_hold(clk, rst, data, data_en));

Anonymous

9 months ago

assert property @change(sig1); time t1= $time; |->$stable(sig1) && $rose(clk); t1- $time == setup_time; |-> $stable(sig1) ; $time - t1+ setup_time >= hold_time;

How would you compose an SVA in System Verilog to verify an input signal adheres to setup and hold time constraints?
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Write an SVA (System Verilog Assertion) to ensure that an input signal does not violate a setup or hold time requirement.

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