Verilog Coding

How would you compose an SVA in System Verilog to verify an input signal adheres to setup and hold time constraints?

Did you come across this question in an interview?

Answers

Anonymous

4 months ago

Anonymous

5 months ago

Interview question asked to Design Verification Engineers interviewing at Harley-Davidson, Continental, NEC and others: How would you compose an SVA in System Verilog to verify an input signal adheres to setup and hold time constraints?.