How would you script an SVA in System Verilog to confirm a FIFO's emptiness prior to executing a read operation?

Question

Anonymous · Accepted Answer

Before we read or on the read request we can check $past of the empty signal.
This can help us previous state of fifo empty or not. If empty assert error

Anonymous · Answer

property p_no_read_on_empty;

@(posedge clk) disable iff (!reset_n)

(read_enable && fifo_empty) |=> $error("Attempted read on empty FIFO!");

endproperty

assert property (p_no_read_on_empty) else $fatal_error("SVA: FIFO read-on-empty
violation!");

How would you script an SVA in System Verilog to confirm a FIFO's emptiness prior to executing a read operation?

Practice this question with AI

Go Premium

Practice More Questions

Community Answers

Unlock Community Insights

Unlock Community Insights