Verilog Coding

How would you script an SVA in System Verilog to confirm a FIFO's emptiness prior to executing a read operation?

Did you come across this question in an interview?

Interview question asked to Design Verification Engineers interviewing at Applied Materials, Broadcom, OMRON and others: How would you script an SVA in System Verilog to confirm a FIFO's emptiness prior to executing a read operation?.