Verilog Coding

How would you draft an SVA in System Verilog to prevent transaction initiation during an active reset signal?

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1 interview answer published by candidate; last submission on Sep 14 2024, 4:25am GMT.Interview question asked to Design Verification Engineers interviewing at STMicroelectronics, Sharp, Bombardier Transportation and others: How would you draft an SVA in System Verilog to prevent transaction initiation during an active reset signal?. Last reported: Apr 27 2025, 10:01am GMT.