Verilog Coding

How would you draft an SVA in System Verilog to prevent transaction initiation during an active reset signal?

Design Verification Engineer

Google

Akamai

Philips

IBM

Zoox

Varian Medical Systems

Did you come across this question in an interview?

Answers

Anonymous

6 months ago
4.6Exceptional
property no_transaction_during_reset;
  logic rst;
  logic transaction_start; // Signal indicating the start of a transaction

  @(posedge clk) 
  disable iff (rst) // Disable the assertion during reset itself
  (rst) |-> ##1 (!transaction_start);
endproperty

assert property (no_transaction_during_reset(rst, transaction_start));
  • How would you draft an SVA in System Verilog to prevent transaction initiation during an active reset signal?
  • Can you demonstrate how to formulate an SVA in System Verilog that prohibits starting a transaction when a reset signal is on?
  • In System Verilog, how do you construct an SVA to block transaction initiation while the reset signal is active?
  • Could you devise an SVA in System Verilog to ensure no transaction begins when a reset signal is ongoing?
  • What method would you employ to create an SVA in System Verilog that stops transactions from starting during an active reset?
  • How do you design an SVA in System Verilog to inhibit transaction initiation during a reset signal's activity?
  • In System Verilog, how would you establish an assertion to prevent transaction commencement while the reset signal is live?
  • Can you outline the approach for setting up an SVA in System Verilog to disallow transactions during an active reset phase?
  • How would you configure an SVA in System Verilog to validate that no transactions kick off during a reset signal's operation?
  • In System Verilog, what's your technique for ensuring through an SVA that transactions don't initiate while the reset is active?
  • Write an SVA (System Verilog Assertion) to ensure that a transaction is not initiated while a reset signal is active.

Interview question asked to Design Verification Engineers interviewing at Zoox, BMW Group, Lam Research and others: How would you draft an SVA in System Verilog to prevent transaction initiation during an active reset signal?.