Verilog Coding
How would you design an SVA in System Verilog to prohibit memory read/write actions during a power-on-reset cycle?
Design Verification Engineer
Honeywell
Panasonic
Philips
Cruise
Analog Devices
Interview question asked to Design Verification Engineers interviewing at Rohde & Schwarz, GlobalFoundries, Huawei and others: How would you design an SVA in System Verilog to prohibit memory read/write actions during a power-on-reset cycle?.