Expert Answer
Anonymous
module sequence_detector(
input clk,
input reset,
input bit_in,
output reg sequence_detected
);
// Define the states
typedef enum logic [1:0] {
S0, // Initial state
S1, // Detected '1'
S2, // Detected '10'
S3 // Detected '101'
} state_t;
state_t current_state, next_state;
// State transition
always @(posedge clk or posedge reset) begin
if (reset)
current_state <= S0;
else
current_state <= next_state;
end
// Next state logic
always @(*) begin
case (current_state)
S0: begin
if (bit_in == 1)
next_state = S1;
else
next_state = S0;
end
S1: begin
if (bit_in == 0)
next_state = S2;
else
next_state = S1;
end
S2: begin
if (bit_in == 1)
next_state = S3;
else
next_state = S0;
end
S3: begin
if (bit_in == 1)
next_state = S1;
else
next_state = S0;
end
default: next_state = S0;
endcase
end
// Output logic
always @(posedge clk or posedge reset) begin
if (reset)
sequence_detected <= 0;
else if (current_state == S3)
sequence_detected <= 1;
else
sequence_detected <= 0;
end
endmodule
