Could you explain the difference between positive edge triggering and negative edge triggering in Verilog?
Design Verification Engineer
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Honeywell
Qualcomm
Samsung
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Answers
Anonymous
6 months ago
For postive edge triggering the signal changes whenever it changes from low to high and for negative edge triggering the signal changes whenever it changes from high to low
Interview question asked to Design Verification Engineers interviewing at Blue Origin, Mentor Graphics, Triumph Motorcycles and others: Could you explain the difference between positive edge triggering and negative edge triggering in Verilog?.