Craft Verilog code to create a positive/negative edge detector.

Design Verification Engineer

Honeywell

Micron Technology

Panasonic

Arm

Cruise

Amgen

Answers

Anonymous

4 months ago
4.6Exceptional
module edge_detector(input clk, input signal, output edge);
    always @(posedge clk) begin
    fork
@(poedge signal) edge <=1;
join_none
fork
@(negedge signal) edge <=0;
join_non
    end
endmodule
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Interview question asked to Design Verification Engineers interviewing at Yamaha Motor Corporation, Corning, Honeywell and others: Craft Verilog code to create a positive/negative edge detector..