What sets apart reg, logic, and wire datatypes in System Verilog?

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Anonymous · Accepted Answer

reg and wire are mainly used in verilog as different datatypes, where logic is
the main datatype used in system verilog and it is compatible with wire and reg
from verilog. logic is a type that can have 1 of 4 values 0 1 X Z that differs
from bit which can have only 2 values : 0 and 1

What sets apart reg, logic, and wire datatypes in System Verilog?

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