Expert Answer
Anonymous
module mod_15_counter (
input wire clk, // Clock signal
input wire reset_n, // Active low reset
output reg [3:0] count // 4-bit counter output
);
// Combinational logic to determine the next valid state
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
count <= 1; // Start from 1 when reset is active
else begin
case (count)
1: count <= 2;
2: count <= 6;
6: count <= 7;
7: count <= 9;
9: count <= 10;
10: count <= 11;
11: count <= 12;
12: count <= 13;
13: count <= 14;
14: count <= 15;
15: count <= 1; // Wrap around to 1 after 15
default: count <= 1; // Default case to start from 1
endcase
end
end
endmodule
module tb_mod_15_counter;
reg clk;
reg reset_n;
wire [3:0] count;
// Instantiate the mod-15 counter
mod_15_counter uut (
.clk(clk),
.reset_n(reset_n),
.count(count)
);
// Clock generation
always #5 clk = ~clk; // Clock period of 10 time units
initial begin
// Initialize signals
clk = 0;
reset_n = 0;
// Apply reset
#10 reset_n = 1;
// Let the simulation run for 200 time units
#200 $stop;
end
// Monitor the output
initial begin
$monitor("Time: %0d, count: %0d", $time, count);
end
endmodule
