Why do you think C is commonly used for creating Verification Models?

Question

Anonymous · Accepted Answer

C models are interfaced easily with dpi calls from System Verilog testbench. C
models are coded up early in project phase along with arch definition that can
be reused for verification later on

Anonymous · Answer

C models can effectively use pointers to build models of registers which are
very similar to the process of how CPU fetch the memory

Why do you think C is commonly used for creating Verification Models?

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